A static random access memory (SRAM) bitcell includes a pair of cross-coupled inverters. Depending upon the binary state of a stored data bit, a p-type metal oxide semiconductor (PMOS) transistor in one of the inverters may charge a true (Q) data node. Similarly, a PMOS transistor in a remaining one of the cross-coupled inverters may charge a complement (QB) data node depending the binary state of the stored data bit. The Q data node couples through a first n-type metal oxide semiconductor (NMOS) access transistor to a bit line whereas the QB data node couples through a second NMOS access transistor to a complement bit line. During a write operation in which the binary content of the bitcell is changed, one of the PMOS transistors will initially be on and charging its data node while an access transistor is attempting to discharge the same data node through the corresponding grounded bit or complement bit line. The access transistor must thus be relatively strong with regard to the PMOS transistor so that the data node can be discharged relatively quickly. To provide this strength, the access transistors may be relatively large as compared to the inverter PMOS transistors. But increasing the size of the access transistors reduces density for the resulting SRAM.
To strengthen the access transistors without such a loss in density, it is thus conventional to provide a negative boost voltage on the otherwise-grounded bit line during the write operation. This negative boost voltage is applied during a write assist period to increase the strength of the access transistor in comparison to the inverter PMOS transistor so that the access transistor can quickly discharge the corresponding data node yet each access transistor may remain relatively small to enhance density. The negative boost voltage is applied during the write assist period through a boost capacitor. But the charge on the boost capacitor is partially discharged to ground at the termination of the write assist period through the write driver.
This discharge of the boost capacitor charge may be better appreciated with regard to a conventional memory 100 shown in FIG. 1. A write driver inverter 115 is in series with another write driver inverter 105. An output of write driver inverter 105 drives a true bit line whereas the data bit input signal (data) drives an input of write driver inverter 115. Write driver inverter 105 includes a p-type metal oxide semiconductor (PMOS) transistor P1 having a source connected to a power supply voltage node supplying a power supply voltage VDD. A drain of transistor P1 connects to a drain of an n-type metal oxide semiconductor (NMOS) transistor M1. The drain nodes for transistors P1 and M1 (the output node for inverter 105) are coupled to the bit line. Similarly, the gates of transistors P1 and M1 from the input node for write driver inverter 105 and are thus connected to the output of write driver inverter 115. The source of transistor M1 connects to ground through an NMOS write assist transistor M3. An inverter 125 inverts a boost enable signal (boost_enb) to drive the gate of write assist transistor M3. In memory 100, the boost enable signal is active high such that it is a binary low value (ground) outside of the write assist period. Prior to the initiation of the write assist period, write assist transistor M3 is thus switched on. Should the data bit have a binary high value, transistor M1 is also switched on such that the true bit line is discharged to ground through transistor M1 and write assist transistor M3.
The output of inverter 125 is delayed through a pair of inverters 130 and 135 in series with inverter 125 to drive an anode of a boost capacitor 140 such as formed by the gate capacitance of a PMOS transistor P3 (both the drain and the source of transistor P3 are connected to the output of inverter 135 to form the anode of boost capacitor 140). The gate of transistor P3 forms the cathode of boost capacitor 140, which is connected to the source for transistor M1. Prior to the initiation of the write assist period, the anode of boost capacitor 140 is charged to the power supply voltage VDD whereas the cathode of boost capacitor 140 is discharged to ground. The assertion (note that as used herein, a signal is deemed to be “asserted” if it is charged high in the case of an active-high signal or discharged in the case of an active-low signal) of the boost enable signal at the initiation of the write assist period is delayed through the pair of inverters 130 and 135 to discharge the anode of boost capacitor 140. The gate capacitance for transistor P3 then pulls its gate voltage below ground to provide a negative write assist voltage boost to the true bit line.
The write driver also includes an write driver inverter 120 in series with another write driver inverter 110. Write driver inverter 120 inverts a complement data bit (data_bar) to drive the input of write driver inverter 110, which is formed by a PMOS transistor P2 in series with an NMOS transistor M2. The source of transistor M2 is tied to the cathode of boost capacitor 140 in common with the source of transistor M1. The output of write driver inverter 110 (the drains of transistors P2 and M2) drives the complement bit line. When the data bit is true, the complement data bit is of course false such that transistor P2 is on and transistor M2 off prior to the write assist period. During the write assist period, the source voltage of transistor M2 is pulled below ground by, for example, as much as half a volt. The gate to source voltage for transistor M2 is thus positive despite the grounding of its gate such that the boost charge from boost capacitor 140 is discharged through transistor M1 and then through transistor P2 into the power supply node at its source. Boost charge is also discharged through the weakly-on transistor M2 into the complement bit line. An analogous discharge through transistor M1 occurs during the write assist period should the data bit input signal be a binary high value. This discharge of the boost charge not only wastes power but also weakens the negative boost for the discharged bit line.
Accordingly, there is a need in the art for memories having an enhanced negative bit line boost with reduced power consumption.